Semiconductor vias include a barrier/liner to protect the metal from oxygen and moisture. A typical barrier/liner thickness in current semiconductor vias is 35 angstroms (Å) at sidewall surfaces and 70 Å at the bottom surface. To reduce via and line resistance, a thinner barrier/liner stack is needed. However, attempts to reduce the thickness have been unsuccessful as they have reduced the barrier properties of the stack. For example, atomic layer deposition (ALD) of tantalum nitride (TaN) followed by physical vapor deposition (PVD) of tantalum (Ta) improves via and possibly line resistance. However, since ALD TaN has much lower density than PVD TaN (currently employed), its barrier property against moisture penetration into the copper (Cu) line from the ultra-low-k (ULK) material used for the interlayer dielectric (ILD) is poorer, thereby challenging EM reliability.
Similarly, PVD TaN with chemical vapor deposition (CVD) of cobalt (Co) or ruthenium (Ru) can thin down the overall barrier/liner stack. However, CVD Co or Ru is not an oxygen/moisture barrier. Accordingly, the PVD TaN must act as the moisture barrier, thereby requiring a thicker TaN layer, which negates the reduction in thickness and resistance. ALD TaN with CVD Co or Ru can achieve the thinnest and most conformal barrier/liner bilayer stack. However, neither ALD TaN nor CVD Co or Ru is a good moisture barrier. Therefore, EM reliability suffers even more than the other approaches. Single layer manganese nitride (MnN) or manganese (Mn) or Mn doped ALD TaN can be formed to thicknesses below 15 Å, but oxidation stress tests indicate that they are inferior to PVD TaN plus Ta.
A need therefore exists for methodology enabling formation of a thin barrier/liner stack without compromising moisture and oxygen barrier properties and the resulting device.